DSP multi SPI port communication design of the hot

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DSP multi SPI port communication design of CPLD

Abstract multi SPI port communication is a small high-speed synchronous communication network. This network has simple structure and low cost, and is widely used in the communication between controllers and between controllers and peripheral chips; However, due to the complex timing, high-frequency pulse transmission data is prone to error. Based on the time sequence analysis of SPI port signal, this paper gives the specific implementation method of the network based on CPLD. The experiment proves that the effect is good


at present, in electrical automation control devices, various communication means are widely used to complete the information transmission between the upper layer and the lower layer controller, the lower layer controller and the control chip, and realize the corresponding control functions; The design and implementation of various communication functions have become an important part of the design of automation devices. Based on the application background of an ultrasonic motor motion control device, this paper discusses the multi SPI port communication technology of DSP control chip based on CPLD

serial synchronous peripheral port (SPI) is usually called synchronous peripheral port. It has the characteristics of few signal lines, simple protocol and fast transmission speed. It is widely used in the communication between microcontroller and peripheral chips. At present, SPI communication mode has been widely accepted, and there are more and more chips with SPI ports, such as flash, ram, a/D conversion, LED display, special DSP chip for control, etc

this paper introduces a motion control device of ultrasonic motor designed with dsp56f801, a special DSP chip for motion control. Because the ultrasonic motor needs two-phase four channel symmetrical PWM signals to realize driving control, and the DSP chip cannot directly generate the required PWM signals, and the software method will occupy a lot of DSP calculation time, a symmetrical PWM signal generator based on programmable logic device (CPLD) is designed. Under the control of DSP, the signal generator can adjust the duty cycle and phase difference of the output two-phase PWM control signal; At the same time, the programmable oscillator ltc6903 with SPI interface is used to realize the frequency adjustment of PWM control signal under the control of DSP. It can be seen that in order to control the duty cycle, phase difference and frequency of PWM control signal by DSP, it is necessary to adopt appropriate communication methods to realize the control information transmission between DSP, CPLD and ltc6903. Dsp56f801 chip has an SPI communication port. Based on the analysis of SPI data transmission timing relationship, this paper designs and implements multi SPI interface communication based on CPLD

1 working principle

spi is a synchronous protocol interface, and all transmissions refer to a common clock. At the same SPI port, one master chip can be connected with multiple slave chips. At this time, the master selects the slave device by triggering the chip selection input pin of the slave device. The slave device that is not selected will not participate in SPI transmission. SPI master uses four signals: master output/slave input (MoSi), master input/slave output (MISO), serial clock signal SCLK and peripheral chip selection signal (SS). Both the host and peripheral devices contain a serial shift register. The host initiates a transmission by writing a byte to its SPI serial shift register. The register transmits bytes to the slave device through the MoSi pin, and the slave device also returns the contents of its shift register to the host through the miso signal line. In this way, the contents of the two shift registers are exchanged. The write and read operations of peripheral devices are completed synchronously, so SPI has become a very effective serial communication protocol. The communication network structure block diagram of SPI port is shown in Figure 1. In order to make the signal generator output two-phase four channel PWM waves with frequency modulation, voltage regulation and phase modulation output, DSP is required to output parameters to CPLD circuit. The transmission of these four control parameters is realized in a small communication network. In this network, the spi of DSP only writes the data output port, that is, outputs voltage control word, phase control word and frequency control word. Data flow: the host DSP transmits data to CPLD. When transmitting data, the data is output on the MoSi pin, and the data is synchronously shifted and output under the action of the clock signal. Since there is no need for the slave to send back any data to the host, the host ends the transmission after the data transmission is completed. Since there is no response signal when the SPI port works, and there is no need to check the bit when sending data, it is required that the data transmission and reception of the master and slave devices must fully meet the set SPI timing requirements, otherwise the data transmission will be wrong

2 serial port SPI design based on CPLD

2.1 shift register design

this design is a 12 bit SPI serial receiving port. In Figure 1, the shift register is composed of 12 d flip flops and a counter to realize shift reception and serial parallel conversion. In the transmission process, first enable the shift register and counter, start the transmission, and the counter starts counting. When the count reaches 16, the carry end outputs a high-level pulse with pulse width for data latch, and its circuit is shown in Figure 2

in order to ensure the correct timing in the experiment, the output timing of the enable signal and the counter carry pulse is measured, as shown in Fig. 3 and Fig. 4. The hexadecimal counter adopts the rising edge counting. When the 16th rising edge arrives, it jumps to high level to ensure the correct receiving and locking of data

2.2 latch design

working characteristics of the latch: when a high-level signal is input on the gate pin, the latch starts to work and latch the data on the bus; When the gate pin is at low level, the latch does not work, that is, when the data on the bus changes, the output of the latch does not change. Since this design requires multiple parameter transmission, these three data are distinguished from a bus by the method of address selection, and the lower two bits of the transmission data are set as the address selection bits. The address selection bit is used as the two inputs of the three input and gate to select the address through the shift register and serial parallel conversion. At the end of each 16 bit data shift and when the data is stable, under the action of the high level of the counter, the high level is output on the pin of the corresponding gate, and the data is locked into the corresponding 3-bit latch. For example, when the lower two bits are 11, the DSP sends the phase modulation signal of ll bit into the PWM circuit; When the lower two bits are set to 01, the DSP sends a 10 bit signal to the PWM circuit to adjust the duty cycle of phase a; When the lower two bits are set to 10, the DSP sends a 10 bit signal to the PWM circuit to adjust the B-phase duty cycle. Thus, a three input and gate can be designed in the circuit. When the 16 bit data transmission is completed, that is, the high level is output on the corresponding gate pin, and the data is stored in the corresponding latch, as shown in Figure 5

2.3 interface configuration between DSP and ltc6903

since the ltc6903 chip itself has SPI interface, it is necessary to set the corresponding SPI register in the DSP program. Ltc6903 adopts rising edge reception, and the high bit is in front when receiving, so DSP needs to be set as falling edge transmission, and the high bit is in front when transmitting. In the process of transmission, when the data changes on the falling edge of the pulse signal, the data is transmitted; The data is stable at the rising edge of the pulse signal, which is convenient for ltc6903 to latch data. The transmission sequence is shown in Figure 6. It can be seen from the figure that the data to be transmitted is the hexadecimal number 019a, the falling edge data changes, the rising edge data is stable, 16 bit data is transmitted, and there are 16 pulses. The experimental results show that the DSP configuration and ltc6903 should be equipped with anti loose installation; The SPI interface works in time sequence

3 SPI development process in DSP

spi port data transmission is characterized by: whether the clock signal of the master device appears or not determines the start of data transmission. Once the clock signal is detected, the transmission starts, and the transmission ends after the clock signal is invalid. During this period, it is important to enable the start and stop status of the clock signal from the device. The start and stop status of the clock signal of the SPI port of dsp56f801 is listed in Table 1. The cpol and CPLA bits of the SPI control register set in the design are 11. SCLK is at high level when idle, and the data changes during transmission occur on the falling edge and stabilize on the rising edge. It can be seen from Figure 2 that the matching with the shift latch circuit in CPLD is realized, and the transmission is correct

spi port protocol requires that after the system is powered on and reset, the slave starts working before the host. If the machine starts working after the host, which is unexpected in the industry, it may lose part of the clock signal, so that the slave does not receive the data from the first place, resulting in the asynchronous data flow. Hardware delay or software delay can be used to ensure that the slave works before the host. This design adopts the method of software delay to realize the synchronization of data flow. This delay consists of two parts, one is the time delay of DSP serial output data, and the other is the delay in the subsequent digital circuit. The specific calculation process of delay is as follows: the clock signal used in data transmission is to divide the bus clock by 2. When the main frequency of DSP is 60 MHz, the bus clock frequency is 30MHz. By dividing it by 2, the cycle of SCLK can be calculated to be 66.6ns (the actually measured cycle is 78.2 NS). In addition, the longest delay of PWM circuit is 23.6 ns, the maximum delay of latch is 7.6 ns, and the maximum delay of shift register is 3.0 ns. From the above delay of CPLD digital circuit and the test of SCLK cycle, we can get such a conclusion: set the delay time of PWM circuit as T1, the delay time of latch as T2, the delay time of shift register as T3, and the clock cycle of SCLK as TC. In the process of SPI transmission, the delay t of the whole circuit can be calculated as follows:

due to such delay in digital circuit transmission, when writing DSP program, A certain delay needs to be added. The delay added in this experiment is 2 s, which can realize reliable transmission

4 experimental results

this design adopts full digital structure and is easy to be realized with CPLD. Taking epm7256 as the target chip, the correct data transmission is designed and realized. When the hexadecimal parameters output by dsp56f801 are frequency word dboe, phase word 0403, duty cycle word 04ce of phase A and duty cycle word 04cd of phase B respectively, the waveform output is shown in Fig. 7 and Fig. 8. Figure 7 shows the measured waveform of the phase a output signal of the signal generator, and the signal duty cycle is adjusted to 20%; Figure 8 shows the measured waveforms of phase a output signal 1 and phase B output signal L, and the phase difference of the two signals is adjusted to the commonly used 90. The experimental results show that the parameter transmission is correct and the waveform output is good


spi communication mode has the advantages of simple hardware connection and convenient use, and is widely used. The combination of hardware and software can ensure the synchronization of data flow in SPI communication and realize reliable communication. This paper presents the design and implementation process of DSP multi SPI port communication, and discusses the key technical problems. SPI multi port communication method is based on CPLD, easy to transplant, easy to realize function expansion, and can be widely used in various automation devices using SPI communication mode

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